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Synopsys Strengthens Design-Technology Co-Optimization Solution with ...

Sep 18, 2017 - Materials Modeling Enables Semiconductor Manufacturers to Save Time and Cost for Advanced Process Node Development

Synopsys and IIT Bombay Announce Release of Sentaurus TCAD Model for NBTI ...

Dec 5, 2016 - Model Developed Through Collaboration Between Synopsys and IIT Bombay to Simulate Negative-Bias Temperature Instability in FinFET and Nanowire FET at 7nm, 5nm and Below

Imec and Synopsys Collaborate on Interconnect Resistivity Model to Enable ...

Jul 11, 2016 - Synopsys' Process Explorer and Raphael accurately simulate parasitic resistance of alternative metals and liner-barrier materials at the 7nm node and beyond

Synopsys Completes Acquisition of Gold Standard Simulations

May 23, 2016 - Acquisition supports the Synopsys TCAD strategy to offer a comprehensive solution to reduce development time and cost for advanced node development by enabling the evaluation and ...

Synopsys Launches Pre-Wafer Simulation Solution to Reduce Semiconductor ...

May 23, 2016 - Enables Earlier Co-Optimization of Devices, Processes, Materials and Design

Synopsys and Imec Expand TCAD Collaboration to 5 nm and Beyond

Dec 16, 2014 - Enables Delivery of Accurate Sentaurus TCAD Models for Nanowire, FinFET and Tunnel-FET Transistors

Synopsys and IIT Bombay Collaborate on Reliability

Jun 30, 2014 - Collaboration enables stochastic modeling of device degradation and reliability through industry leading Sentaurus Device TCAD simulator