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DTCO: Screening and Selection of New Interconnect Metals with QuantumATK

Apr 5, 2019 - In the context of DTCO, new interconnect metals not only offer the promise of reduced parasitic loading in the MOL but also enable the integration of new scaling boosters such as ...

Synopsys DTCO Flow: Technology Development

Feb 1, 2019 - DTCO can be aptly described as a software-based methodology for developing new semiconductor process nodes with a holistic consideration of how technology elements impact circuit ...

IBM and Synopsys Accelerate 3nm Process Development with DTCO Innovations

Aug 15, 2018 - Synopsys Manufacturing, IP, and Design Implementation Technologies Enable Industry's Only Complete DTCO Flow

Sentaurus TCAD New Release Update

Aug 9, 2018 - The O-2018.06 version of the Sentaurus suite of TCAD process and device simulation tools was released in June 2018. This webinar will provide an overview of important updates in this ...

Sentaurus Lithography

Sentaurus Lithography represents advanced modeling for semiconductor device manufacturing process development and optimization, covering a wide-range of applications in optical, immersion, EUV, and...

Proteus WorkBench

Proteus WorkBench provides a single tool environment that facilitates building models, tuning correction recipes for full-chip OPC, and analyzing proximity effects on corrected and uncorrected IC ...

Proteus

Proteus provides a comprehensive and powerful environment for performing full-chip proximity correction, building models for correction, and analyzing proximity effects on corrected and uncorrected...

Proteus Inverse Lithography Technology (ILT)

Advanced Correction of Optical Proximity Effects

Sentaurus Lithography PWA

Sentaurus Lithography process window analyzer (PWA) is a comprehensive and powerful tool for visualizing and analyzing simulation results or experimental data, for example, obtained by critical ...

IC WorkBench Edit/View Plus

Powerful, hierarchical layout visualization and analysis tool, which allows viewing and editing GDSII and OASIS layouts from small IP blocks to full chip databases